The invention is generally related to processing of printed circuit boards, and more particularly, to the processing of printed circuit boards that include an area array assembly, such as Land Grid Array (LGA).
As silicon technology advances, there is a trend for higher density electrical interconnection of components on a circuit board or Printed Wiring Board (PWB). Increasingly, Pin Through Hole (PTH) attachment of electronic components is inadequate due to the limited number of interconnections possible thereby. The hole prevents overlaying separate conduction paths. In addition, practical dimensions of the holes and pins for inserting in the holes further limits PTH attachment to low density electronic components.
xe2x80x9cStandardxe2x80x9d Surface Mount Technology (SMT) is used often used when PTH is not applicable or not desired, such as when interconnecting components having lead pitches of approximately 50 mils (1.27 mm). Surface Mount Technology allows overlaying multiple conduction paths across a given point on the circuit board and can be used on both sides of the circuit board. Multiple SMT components are typically placed on an upward face of a circuit board prepared with solder paste printing. The leads of the SMT components are simultaneously attached through a mass reflow process where an infrared heat source melts the solder paste printing to electrically and mechanically attach the leads to the circuit board.
With more complex microprocessors and higher throughput Application Specific Integrated Circuits (ASIC), Fine Pitch Technology (FPT) interconnect components having peripheral leads having a pitch ranging from about 20-40 mils (0.5-1.0 mm) are used. FPT is based on 50 mil standard SMT production, but with minor changes and tighter process controls.
Ultra-Fine Pitch Technology (UFPT) enables interconnection of components having hundreds of peripheral leads with lead pitches of about 0.5 mm (20 mils) or less. For higher lead counts ranging from hundreds to thousands of leads, area array packaging techniques are used, and are characterized as having a group of connection elements, such as solder bumps or alternate interconnect pads arranged as rows and columns beneath a component package body.
For solderable array packages, such as Ball Grid Array (BGA) and micro-BGA area integrated circuit packages, the input and output points are solder balls arranged in a grid pattern on the underside of the component. However, cyclic temperature variations in applications can pose solder fatigue reliability problems to the ball solder connections. Interconnections with less sensitivity to cyclic temperature fatigue include Column Grid Array (CGA) in which solder columns are used rather than solder balls.
Land Grid Arrays (LGA) are often used for high lead count packaging that have interconnection requirements where solder connection cannot provide adequate reliability. LGA is also often used when a capability is desired for readily replacing a component or modules onto the circuit board without costly and time consuming solder repair and assembly processes, thus enhancing the repairability and upgradeability of a circuit board. Land Grid Arrays (LGA) are integrated circuit (IC) packages (e.g., an LGA socket) in which conductive bumps in an array are mechanically held without the use of solder by an LGA interposer to corresponding conductive terminal pads that form the bonding site on the circuit board. Consequently, the LGA packaging is not subjected to the temperature expansion of BGA and CGA packaging during reflow and thus finer lead pitches are achievable.
Area array packages drive different requirements on the circuit board for surface finish and assembly, unlike PTH and standard SMT packages. For example, Ball Grid Array (BGA), Column Grid Array (CGA), and Land Grid Array (LGA) each have a requirement for coplanarity of bonding sites not necessarily accommodated by generally used solderable surfaces. Moreover, depending on the type of array packaging used, surface treatment of the bonding site on the circuit board, such as by Organic Surface Preparation (OSP) or gold plating, is required to ensure interconnection reliability of LGA termination. Specifically, to ensure LGA interconnection reliability, LGA surface treatment of the circuit board must include noble metal plated (e.g., gold/nickel) terminal pads at the bonding site.
Area array surface finish treatments should be kept free of contaminants to ensure reliable electrical interconnection of the attached area array component, such as an LGA socket. Since a circuit board may include other components assembled by PTH attachment and standard SMT and FPT, keeping the surface finish clean and free of contaminants may be difficult due to the number of circuit board fabrication processes that may occur between the time that the surface finish is applied and the area array components are affixed to the circuit board. These bonding sites are thus subject to contamination during PWB fabrication, including presence of resist or mask residues. These bonding sites are further subject to contamination during assembly including presence of flux residues, solder transfer, and various adherent or semi-adherent organic and inorganic residues transferred to the bonding site during all phases of circuit board handling, assembly, test and repair operations. Avoiding contamination is particularly significant for an LGA assembly where an LGA interposer presses the LGA component into electrical contact with the surface treated bonding site, rather than having a solder contact wherein the melting of the solder may overcome surface contaminants. The LGA interposer grips the circuit board and self aligns to the bond site through apertures in the circuit board.
Conventionally, area array bonding sites have been protected during various processing steps through the temporary application of an adhesive film, e.g., a KAPTON(copyright) tape having a silicone-based adhesive available from Du Pont. However, protection of the bonding sites with tape masking may introduce a source of contamination when a portion of the tape, or the adhesive residue from the tape, remains on the bonding site.
Residue from adhesive tape may entrap fluids during processing of the circuit board, such as during cleaning. Also, residue may encourage condensation and retention of water thereafter. The tape residue itself, or contaminants entrapped during processing of the circuit board, may also detrimentally chemically react with the circuit board. For example, presence of contamination on the surface treatment can create conditions for both electrochemical corrosion and metal migration allowing for either oxidized, insulating layers to form on a bonding site, or growth of conductive metal filaments between separate interconnection paths. Applications and removal of adhesive tape can also cause slivers of metal to be dislodged on the circuit board, such as removing and redepositing gold LGA terminal pads from the bonding site.
Therefore, aggregate contaminations can create either open circuits between an area array contact and a bonding site, or short circuits across adjacent contacts. The defects may be immediate, or dependent on factors such as temperature, frequency of a signal utilizing the contact, humidity, vibration, etc., and thus be intermittent. The defects may also be latent, such as a contaminant that oxidizes over time becoming insulating.
In addition to potential for generation of LGA contact defects, a masking process is constrained by the time required to place and remove the tape, as well as additional steps of inspection and test required to verify correct removal, thus increasing production costs.
Consequently, a significant need exists for protecting area array surface treated bonding sites during assembly processing of a printed circuit board.
The invention addresses these and other problems associated with the prior art by providing an apparatus and method of protectively covering a bonding site on a circuit board during processing using a combination of a protective cover and a plurality of posts that engage and align the cover over an area array bonding site of a printed circuit board.
In many embodiments, adhesive is not required to effectively retain the protective cover in position over the bonding site. Thus, the protective cover does not leave residue on the bonding surface like tape or film that are prone to failure during removal, especially with the increased removal forces required to overcome the adhesive. Consequently, the protective cover does not become a source of contamination to the bonding site from residue of the adhesive or a failed portion of the protective cover.
Consistent with one aspect of the invention, a method for processing a circuit board having an area array bonding site includes overlaying a protective cover over the bonding site by registering a plurality of posts secured to one of the protective cover and the circuit board into a plurality of apertures disposed in the other of the protective cover and the circuit board. With the protective cover overlaid on the circuit board, various fabrication processes may then be performed and then the protective cover is removed.
Consistent with an additional aspect of the invention, an assembly of a circuit board having an area array bonding site on a surface of the circuit board is overlaid by a protective cover. The protective cover is removably registered to the bonding site by a plurality of posts secured to one of the protective cover and the circuit board into a plurality of apertures disposed in the other of the protective cover and the circuit board.
Consistent with another aspect of the invention, a method of fabricating a protective cover and an assembly of the protective cover and circuit board is described. The circuit board has a plurality of apertures forming a footprint encompassing an area array bonding site on a surface of the circuit board. Base material is sized for the footprint and a plurality of posts are bonded to the base material in a pattern corresponding to the footprint to form the protective cover.
Consistent with yet another aspect of the invention, a cover has a base member shaped to at least correspond to an area array bonding site on a surface of a circuit board. The cover has a plurality of posts coupled to a face and registered for a plurality of apertures on the circuit board.
These and other advantages and features, which characterize the invention, are set forth in the claims annexed hereto and forming a further part hereof. However, for a better understanding of the invention, and of the advantages and objectives attained through its use, reference should be made to the Drawings, and to the accompanying descriptive matter, in which there is described exemplary embodiments of the invention.